1. Technical Field
The present application relates generally to an improved integrated circuit device. More specifically, the present application is directed to a low inductance via arrangement for multilayer ceramic substrates.
2. Description of Related Art
A decoupling network is an electrical circuit arrangement that prevents signals that are applied to one portion of the electrical circuit from affecting other devices or portions of the electrical circuit to which the signal is not applied. The use of such decoupling networks is important in the formation of integrated circuit devices which, because of their compact and ever decreasing size, are prone to having one portion of the integrated circuit negatively affecting other portions of the integrated circuit.
A general goal in the design of a decoupling network is the reduction of inductance. Inductance is a parasitic property of the decoupling network that limits the effect of capacitors at higher frequencies. In a multilayer ceramic package of an integrated circuit device, the inductance has three main contributors: (1) the capacitor's internal inductance; (2) the via-field inductance; and (3) the power plane inductance. With regard to the influence of the via-field inductance on the overall inductance of the capacitor, an exemplary capacitor connection arrangement will be discussed.
FIG. 1 is an exemplary diagram of a known arrangement for connecting a top surface metallization (TSM) capacitor of a multilayer ceramic (MLC) substrate to ground and voltage planes of the MLC. As shown in FIG. 1, the capacitor has eight surface pad connections 110-124 assigned to voltage (VDD) or ground (GND) in an alternating pattern. For example, in the depicted arrangement, surface pad connections 110, 114, 120, and 124 are assigned to the VDD net while surface pad connections 112, 116, 118 and 122 are assigned to the GND net. That is, vias for surface pads connections that are assigned to the VDD net selectively contact the VDD connections in the VDD planes while selectively avoiding contact with the GND nets in the GND planes of the MLC substrate. Similarly, the vias for surface pad connections that are assigned to the GND net selectively contact the GND connections in the GND planes while selectively avoiding contact with the VDD nets in the VDD planes of the MLC substrate. Each surface pad connection 110-124 is attached to three vias, e.g., vias 132-136, that connect the surface pads 110-124 to the internal VDD and GND planes of the MLC.
FIG. 2 is an exemplary diagram illustrating a cross-sectional view of the known arrangement in FIG. 1 which illustrates the vias for connecting the TSM capacitor to internal planes. As shown, the standard implementation utilizes straight vias that connect the capacitor's TSM pad connections 110-124 to the VDD and GND plane meshes.
Inductance is a property of magnetic flux generated by a current. For adjacent conductors having oppositely directed current flows, the smaller relative spacing between the conductors reduces the per unit length inductance exhibited by each of such adjacent conductors. Thus, straight vias situated at relatively large surface pad spacing distances represent the least beneficial arrangement of vias with regard to reducing the inductance of the capacitor since the distance between vias is maximized in such an arrangement.